This technology relates a semiconductor device and a fabrication method therefor, and more particularly to a semiconductor device which includes a plurality of field effect transistors (FETs) formed on different substrates and are electrically connected to each other and a fabrication method for the semiconductor device.
In a semiconductor device, the size of a semiconductor element such as a FET is reduced in accordance with the scaling law of Moore to improve characteristics such as a processing speed and power consumption. However, in a semiconductor device, as further reduction in size and further improvement in performance proceed, how to connect semiconductor elements to each other efficiently has become important.
Particularly with regard to a semiconductor device of a three-dimensional structure wherein a plurality of substrates are layered in order to stack a plurality of substrates to improve the degree of integration, various element connection methods have been investigated. Further, the demand for layering substrates is increasing for a case in which transistors which cannot be formed on the same substrate by the same process are integrated in order to improve the performance or for a like case.
One of backgrounds of increase of such cases as described above may be that the difficulty in improvement in performance is increasing, for example, from such a factor as a short channel effect.
In order to overcome the difficulty described, for example, it has been proposed to apply stress to the channel region to produce a strain thereby to improve the carrier mobility to increase the on-state current.
In particular, it is known to cover a FET with a stress liner layer to produce a strain in the channel region. Here, a stress liner layer which applies tensile stress to the channel region of an n-type MOS (Metal Oxide Semiconductor) FET is used to improve the electron mobility. Meanwhile, for a p-type MOSFET, a stress liner layer which applies a compressive stress to improve the hole mobility (refer to H. S. Yang et al., “Dual Stress Liner for High Performance Sub-45 nm Gate Length SOI CMOS Manufacturing,” IEDM Tech. Dig., p. 1075, 2004 (hereinafter referred to as Non-Patent Document 1) or Japanese Patent Laid-Open No. 2010-205951, paragraphs [0030], [0031] and so forth (hereinafter referred to as Patent Document 1)).
Further, it has been proposed to use an epitaxial layer of a grating constant different from that of a semiconductor substrate to form a pair of source-drain regions to apply a strain to the channel region. For example, in an n-type MOSFET, a material which applies a tensile stress such as SIC is used to form a pair of source-drain regions. On the other hand, in a p-type MOSFET, a material which applies a compressive stress such as SiGe is used to form a pair of source-drain regions (refer to, for example, Japanese Patent Laid-Open No. 2006-203091, paragraph [0076], FIG. 7 and so forth (hereinafter referred to as Patent Document 2)).
Further, it is known to form a FET such that a channel region is provided on a crystal orientation plane of a semiconductor having high carrier mobility. For example, an n-type MOSFET is formed such that the “(100)” plane is used as the channel region to improve the electron mobility. On the other hand, a p-type MOSFET is formed such that, for example, the (110) plane is used as the channel region to improve the hole mobility (refer to, for example, M. Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientation,” IEDM, pp. 453-456, 2003 (hereinafter referred to as Non-Patent Document 2) and Japanese Patent Laid-Open No. 2007-194337, paragraph [0003] and so forth (hereinafter referred to as Patent Document 3)).
Further, as reduction of the thickness of the gate insulating film proceeds, gate leak current is sometimes created to cause such a failure that the power consumption increases or the like.
It has been proposed to a high dielectric constant material, that is, a high-k material, having a dielectric constant higher than that of silicon oxide to form a gate insulating film in order to prevent such a failure as described above. For example, the gate insulation film is formed using HfSiON and so on as a high-k material. In the case where a high-k material is used to form a gate insulating film, in order to cause the feature to be exhibited, the gate electrode is formed not from polycrystalline silicon but from a metal material. Here, for the control of a threshold voltage Vth of a FET, an n-type MOSFET and a p-type MOSFET are formed from metal materials different from each other such that appropriate work functions are obtained for gate voltages of the n-type MOSFET and the p-type MOSFET. More particularly, in the n-type MOSFET, the gate electrode is formed using a metal with which the work function of the gate electrode is positioned at an end of the conduction band. Meanwhile, in the p-type MOSFET, the gate electrode is formed using a metal with which the work function of the gate electrode is positioned at an end of the valence band (refer to, for example, L. Witters et al., “8 {acute over (Å)} Tinv Gate-First Dual Channel Technology Achieving Low-Vt High Performance,” IEEE, 2010 (hereinafter referred to as Non-Patent Document 3) and Japanese Patent Laid-Open No. 2005-285809, paragraphs [0002], [0134], [0139] and so forth (hereinafter referred to as Patent Document 4)).